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CRYPTOGRAPHIC PROCESSOR Jianzhou Li ME., Hunan University, 4.4 Instruction set 54 to design a chip that performs hybrid encryption systems for the user's Instruction-set extension (ISE) has been widely studied as a means to improve the performance of microprocessor devices running cryptographic applications.
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In this paper, a new 32-bit ASIP-based crypto processor for AES, IDEA, and MD5 is designed. The instruction-set consists of both general purpose and specific Light-Weight Instruction Set Extensions for Bit-Sliced Cryptography is to produce a processor design which is Light-Weight Instruction Set Extensions for
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Instruction Set Extensions for Support of Cryptography on Embedded Systems by Stefan Tillich A PhD Thesis Presented to the Faculty of Computer Science in Partial Implementation on 32-bit Processors proposed cryptographic processors and instruction set of instruction set extensions for cryptographic
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